cognitoraedge ai
Small computers for robots, home inference and local language models. On small hardware, token speed is set by memory bandwidth, not by TOPS, so that is where the budget goes: a 64-bit LPDDR5 bus on every host, and 3D-stacked DRAM beside the accelerator where the price allows.
The thesis
A language model generates one token at a time. For each token the accelerator reads every weight once, plus the KV cache built so far, at about two operations per byte. Speed follows memory bandwidth:
On the RK3588, llama.cpp runs a 1 GB model at 22.6 tokens/s and a 4.7 GB model at 5.4 tokens/s. Both work out to 22 to 25 GB/s. More TOPS does not change these numbers; more bandwidth does.
DRAM prices rose sharply through 2026, to about $13 per GB. Capacity picks the model; bandwidth picks the speed.
Product family
Every board shares the same software stack, the same memory hierarchy and the same real-time MCU for robotics I/O.
Edge Nano
Edge Node
Edge TowerBOM includes assembly at 10k units with LPDDR at about $13.4 per GB. Board specifications are design targets; the whitepaper marks every figure as measured or estimated.
Edge Tower
Instead of a heatsink and a small fan on every chip, every hot chip in the tower presses onto one shared finned core, and one slow fan moves all the air.
A 100 mm square aluminium extrusion with 28 radial fins runs up the middle of the tower.
Each Edge Node stands in a slot on the dock board in the base, 16 mm from one face of the core, components facing the core. The dock carries power, the LINK ring and a switch to the one LAN port in the base bay.
The RK3588, the on-board RK1828 and the M.2 RK1828 press onto pedestals through 0.5 mm thermal pads.
A 140 mm fan in a 150 mm round frame pulls air in through the grille in the base, through the dock's opening and up through the fins: about 140 W average and 284 W peak for four nodes.
Hardware status
The first hardware is a carrier for a bought-in compute module, for each board. The module brings a working SoC, DRAM and accelerator. That lets the first spin test everything the carrier adds: power, I/O, the board controller, the accelerator power path, mechanics and thermals.
| Edge Node EVT | Edge Nano EVT | Edge Tower dock EVT | |
|---|---|---|---|
| Host module | Turing RK1 (RK3588) on a 260-pin SO-DIMM | Radxa CM5 (RK3588S2), CM4-format connector | None: four slots for the Edge Nodes |
| Accelerator | 2x DFRobot DFR1263 (RK1828) on M.2, switched 12 V per card | ||
| Board | 160 x 100 mm, 6 layers, full-length x16 card edge for the dock | 68.85 x 53.34 mm, 4 layers, two-sided | 172 mm round, 4 layers; its connectors are on a 100 x 41 mm I/O board in the base bay (XT60, RJ45, 2x USB-C) |
| Board controller | STM32G474: power sequencing, fan, temperature, CAN-FD | STM32L552: expansion headers, Qwiic | KSZ9567 5-port switch, USB2514B hub |
| EVT unit cost | about $1,003 with modules, $126 for the carrier | about $122 with module, $42 for the carrier | about $110 built, I/O board about $20 |
Generated KiCad projects with pinouts and sub-circuits from open reference designs. ERC clean, netlists verified.
Placement DRC clean, first-pass routing, every part with an MPN and a distributor price, order files for JLCPCB and PCBWay. Printed enclosure and machined core as CAD, and a build list for the whole tower.
Hand-route the PCIe, USB 3, CSI-2 and Ethernet pairs, order the boards, bring them up, then build a four-node tower.